This comprehensive review explores dynamic on-resistance degradation in GaN power HEMTs and strategies for mitigation.
Gallium nitride (GaN)-based high-electron mobility transistors (HEMTs) are heralding a new era in power electronics, offering high power density, fast switching speed, and high efficiency. In power switching applications, however, the performance of systems employing GaN power HEMTs is significantly impacted by dynamic on-resistance (R ON ) degradation. This phenomenon poses a critical challenge by increasing conduction loss and reducing the practical benefits of GaN technology. This paper provides a comprehensive overview of the mechanisms behind dynamic R ON degradation and explores various strategies to mitigate this issue. Through a detailed analysis, the effects of buffer trapping/detrapping, surface and passivation-interface trapping, hot-electron effects under hard-switching conditions, and threshold voltage (V TH ) instability under different stress conditions are discussed, which indicates that dynamic R ON degradation arises from the coupled response of multiple trap locations and operating conditions rather than from a single trap species, with stress waveform, switching frequency, dv/dt, temperature, and thermal cycling. Furthermore, this review compares optimization techniques for dynamic R ON suppression, including buffer engineering, surface passivation, field-plate design, gate-stack stabilization, device-structure optimization, and low-thermal-budget processing. By linking physical mechanisms, characterization methods, and optimization routes, this review provides a systematic framework for understanding and reducing dynamic R ON degradation in GaN power HEMTs, paving the way for more reliable and efficient commercial power electronic systems.
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Chen et al. (2026) studied this question.
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