Toward full relaxation of sSOI substrates for PFET device fabrication

The new generation of 10 nm FDSOI requires more performance enhancers to increase mobility in the channels, where electron mobility is improved by tensile stress for nMOS and hole mobility is improved by compressive stress for pMOS. Therefore, strained silicon-on-insulator (sSOI) wafers are considered to improve nMOS performance. In the case of using sSOI wafers, relaxing the tensile silicon for PMOS appears to be beneficial to facilitate the Ge condensation process. In this paper, we demonstrate over 90 % relaxation from a 1.25 GPa tensile sSOI starting wafer. Multiple iterations of ion implantation and annealing are also investigated and may provide a path for further relaxation.