A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization

A 5-bit 4.8 GS/s 4-way time-interleaved ADC is designed for a receiver front-end in a 0.13 mum CMOS technology. Each time-interleaved ADC uses look-ahead pipelined stages to enable higher sample rates and more linear residue characteristics than a conventional pipeline ADC. At 1.2 GHz per path, the residue amplifiers settle to 75% of their final value, however, the linear residue characteristics allows using digital reference calibration to enable 30.4 dB of SNDR with a 1.2 MHz input signal. A capacitor pre-charging technique reduces the memory effect errors of the incompletely settled residue to 2% of the stage output swing. The peak INL and DNL are measured as 0.65LSB and 0.55LSB, respectively. The measured ERBW is ~6.1 GHz. The ADC, including the reference buffers, consumes 300 mW from a 1.2-V supply while operating at 4.8 GHz conversion rate. A stage-by-stage feedback compensates the possible bandwidth limitation of the system using a per-stage speculative DFE. The DFE tap is adjustable between 0 and 0.4 using 8 control bits.