This paper describes a low-power piecewise linear A/D converter. A 5 MHz @ 5 V with 25 mW power consumption prototype has been implemented in a 1.5 /spl mu/m CMOS process. The die area excluding pads is 5 mm/sup 2/. 11-bit absolute accuracy is obtained with a new DC offset plus charge-injection compensation technique used in the comparators scheme. This ADC with large dynamic range and high resolution is developed for the readout of a tracker and/or preshower in the future LHC experiments.>
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Valenčic et al. (1995) studied this question.
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