A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC

A byte-wide I/O cell with 660 MB/s data rate uses low-jitter DLL-generated clocks, self-calibrated controlled-current drivers, and linear amplifier input receivers. The CAD techniques developed allow the design to be ported to CMOS processes ranging from 0.7 /spl mu/m to 0.3 /spl mu/m. The chip is 0.9/spl times/3.4 mm/sup 2/ using 0.3 /spl mu/m rules.