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Experimental study demonstrates threshold voltage reduction in p-MISFET gate stacks using a PVD-TiN diffusion barrier, suggesting an effective path to optimize device performance.
The effects of the diffusion control technique by inserting physical vapor deposition (PVD)-TiN film between poly-Si and CVD-TiN films on the properties of p-MISFETs using poly-Si/TiN/HfSiON gate stacks have been studied. This insertion was effective in suppressing the diffusion of Si from poly-Si to HfSiON and was able to reduce the Vthvalue by 0.12 V while keeping the equivalent oxide thickness and S value constant, when the thicknesses of the PVD and CVD-TiN films were 10 and 5 nm, respectively. Although too much ion implantation of fluorine into the substrate deteriorates S value and ION, it was verified that this diffusion control technique, in conjunction with a moderate substrate fluorine implantation, provided a reduction of Vthin pMIS without a deterioration of ION.
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Kawahara et al. (2007) studied this question.
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