A Process and Temperature Insensitive CMOS Linear TIA for 100 Gb/s/λ PAM-4 Optical Links

A linear transimpedance amplifier (TIA) for a 53 GBd PAM-4 optical link to support 100 Gb/s data on a single wavelength is reported. Designed in a 16 nm FinFET CMOS process, the chip consumes 60.8 mW with <; 2% total harmonic distortion (THD), while producing a 600 mVpk-pk differential output, a -3 dB bandwidth of 27 GHz, and an input referred noise density of 16.7 pA/ √Hz. Transimpedance can be programed from 62 to 83 dBQ in 0.5 dBQ steps to enable digital automatic gain control. Novel circuit topologies for high-bandwidth, low-noise, low-power, and high-linearity are discussed in detail. The entire signal path is realized with dc-coupled CMOS inverters biased at mid-supply to achieve maximum gain linearity. Dynamic voltage scaling tightly controls the transimpedance value, bandwidth, and in-band peaking across process, temperature, and voltage (PVT) variations to realize a robust macro with a high parametric yield needed in a system-on-chip.