A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F/sup 2/ cell [CMOS design]

The 6F/sup 2/ cell is widely known for its small area, but its sensing is unstable due to the large array noise. A new low-noise sensing scheme for a 6F/sup 2/ DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises. The bit-line noise is reduced to 85% of that of a conventional scheme with only 0.05% area overhead, which is negligible compared to the area saving by using a 6F/sup 2/ cell. The total chip area and the sensing time can he reduced to 85 and 87%, respectively, compared to conventional DRAM. A 2 kbit DRAM test chip with a 6F/sup 2/ cell Is fabricated using 256 M DRAM technology, and its stable operations are confirmed.