A high performance 16 Mb DRAM using giga-bit technologies

An experimental high performance 16 Mb Dynamic Random Access Memory (DRAM) having a 0.18 /spl mu/m design rule for gigabit DRAM's was developed. Junction leakage current and junction capacitance were reduced by shallow trench isolation (STI). A fast access time even at low operation voltage (1.5 V) was achieved by using a TiSi/sub 2/ gate and new circuit techniques. Large sensing margin and stable operation were achieved by using a new dielectric material (Ta/sub 2/O/sub 5/) in the cell capacitor. Insufficient depth of focus margin for the back-end of line process was overcome by a triple metallization scheme with one W and two Al metals. With these new technologies, a high speed of 28 ns row address access time (T/sub rac/) at 1.5 V and a small chip size of 5.3/spl times/5.4 mm/sup 2/ were achieved.