Random addressable 2048×2048 active pixel image sensor

In this paper, we discuss the design, design issues, fabrication, and performance of a 2048/spl times/2048 active pixel image sensor in a 0.5-/spl mu/m standard CMOS process. Each pixel, 7.5/spl times/7.5 /spl mu/m/sup 2/, consists of three transistors and a photo diode, resulting in a 12-million transistor chip with a die size of 16.3/spl times/16.5 mm. The pixel has a nonintegrating direct readout architecture, with a logarithmic light-to-voltage conversion. This allows the array to be fully random accessible, both in space and time. The sensor has eight analog outputs, each with a pixel rate of 4.5 MHz, which implies a maximum frame rate of eight full frames per second. Sub-sampling or windowing makes higher frame rates possible. The yield of the sensor is high if one accepts a small number of bad pixels.