Design of Variation-Tolerant 1F-1T Memory Array for Neuromorphic Computing

This is the authors' abstract. We don't add key points for this paper.

This letter proposes a memory cell, denoted by 1F-1T, consisting of a ferroelectric field-effect transistor (Fe-FET) cascoded with another current-limiting transistor (T). The transistor reduces the impact of drain current (Id) variations by limiting the on-state current in FeFET, denoted by 1F. We have fabricated 28nm high-k-meta-gate (HKMG) based FeFETs, and the experimental data is used to model and simulate single-cell and memory arrays. The simulation shows significant improvement in bit-line (BL) current (IBL ) variation for 1F-1T memory array. Finally, the system-level neuromorphic simulation with 1F-1T synapses shows an inference accuracy of 97.6% for MNIST hand-written digits with multi-layer perceptron (MLP) neural networks.