Nonvolatile memory cells based on solid electrolytes have many desirable attributes, including low-voltage and low-current operation and a simple process that allows them to be integrated with conventional CMOS processes with minimal additional masking layers. In this paper, we present a 2-kb memory block/testbed (1024 elements) using solid electrolyte cells. The compact memory design addresses many of the unusual operational issues associated with the solid electrolyte elements and allows for two digital bits to be stored and read from each cell with minimal circuitry. The design was fabricated in 0.18-mum CMOS technology and the simulation and physical data are presented. Multilevel-cell (MLC) operation was demonstrated for a 10-muA reference current with a 437-ns cycle time and sub-40-ns access times
No takes yet. Share an insight, caveat, or question.
Gilbert et al. (2007) studied this question.
Synapse has enriched 5 related papers. Consider them for comparative context: