A ±5-V CMOS analog multiplier

A four-quadrant CMOS analog multiplier is presented. The device is nominally biased with /spl plusmn/5-V supplies, has identical full-scale single-ended x and y inputs of /spl plusmn/4 V, and exhibits less than 0.5% nonlinear error at 75% of full-scale swing. Operation with supplies as low as /spl plusmn/2.5 V is also possible. A comparison of theoretical and experimental results obtained from fabrication of the multiplier in a 3-/spl mu/m p-well CMOS process is made.