Limitations of the High–Low C –V Technique for MOS Interfaces With Large Time Constant Dispersion

We discuss the limitations of the high-lowCVtechnique in evaluating the interface trap density (DIT) in MOS samples with a large time constant dispersion, as occurs in silicon carbide (SiC). We show that the high-low technique can seriously underestimateDITfor samples with large time constant dispersion, even if elevated temperatures are used to extend the range of validity.