Optimization-based transistor sizing

A combined heuristic and mathematical programming approach to transistor sizing is presented. A fast heuristic algorithm is used to obtain an initial sizing of the circuit and convert the transistor sizing problem into a nonlinear optimization problem. The problem is then solved, in spaces of reduced dimensionality, by mathematical programming techniques. To cope with the nondifferentiability of the circuit delays, the concept of generalized gradients is proposed to compute the delay sensitivities. Experiments justify the use of this sensitivity computation technique and show that the approach is a good compromise between the speed of the heuristic algorithm and the power of mathematical programming.>