Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop

This paper presents a new algorithm and circuit implementation for high-speed frequency-to-voltage converters (FVC). The proposed system overcomes the deficiencies of a previously reported converter and can operate about 20 times faster. To validate this FVC and show its usefulness, it was used in the design of a frequency locked loop. For the design of this loop, it was found that existing analytical models were incomplete in that they neglect the delay associated to frequency measurements. We proposed a new model which, unlike previous work, shows that frequency locked loops can potentially be unstable. Simulations confirm this fact and also show that the proposed implementation can operate at 5 GHz. To validate the results, a prototype circuit has been fabricated in a 0.18-mum CMOS technology. Tests performed on the prototype show that it runs reliably at 3.84 GHz and consumes 77.4 mW with a 1.8-V power supply when biasing circuitry is included.