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In this work, we studied the thermal stability of a plasma- passivated gate stack for high speed metal-oxide-semiconductor field effect transistor (MOSFET) application, and results show excellent thermal stability up to with negligible changes in the equivalent oxide thickness, interface trap densities , and subthreshold slope. An increase in leakage current ( at ) after anneal can be attributed to the localized thinning of the gate dielectric and the rough interface caused by the out-diffusion of Ga/As, as observed by transmission electron microscopy and energy dispersion X-ray analysis. measurement by the charge-trapping method showed suppressed at the upper half of the bandgap for plasma- passivated devices, which is favorable for n-channel MOSFET operation.
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Suleiman et al. (2010) studied this question.
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