MOS large-scale-integration circuits (LSIs), having advanced remarkably during the past 25 years, are expected to continue to progress well into the next century. The progress has been driven by the downsizing of the components in an LSI, such as MOSFETs. However, even before the downsizing of MOSFETs reaches its fundamental limit, the downsizing is expected to encounter severe technological and economic problems at the beginning of next century when the minimum feature size of LSIs is going to shift to 0.1 and sub-0.1 /spl mu/m. In this paper, the anticipated difficulties and some concepts for 0.1- and sub-0.1 /spl mu/m LSIs are explained based on the research of the downsizing MOSFET into such a dimension, and a further concept for deep sub-0.1-/spl mu/m LSIs is described.
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Hiroshi Iwai (1999) studied this question.
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