Analysis and Optimization of the Back-Gate Effect on Lateral High-Voltage SOI Devices

This paper discusses for the first time the impact of the back-gate bias on lateral DMOS (LDMOS) transistors on silicon-on-insulator (SOI) substrates. An analytical model that takes the back-gate bias and the device parameters into account is presented and verified with a 0.8-/spl mu/m, 80-V SOI smart power technology. It will be explained that the effect of the back-gate bias on the LDPMOS devices is directly opposed to the LDnMOS transistors. The p-channel and the n-channel devices require different design strategies for the optimal buried oxide thickness due to the effect of the back-gate. A new device structure, namely body buried oxide step structure (BBOSS) that locally weakens the effect of the back-gate is presented. The proposed new structure allows a separated optimization of the buried oxide thickness without affecting the on-resistance.