Enhancing HfO 2 -Based Si Channel FeFET Retention by Tunneling Barrier Engineering: Inserting Al 2 O 3 Layers to Increase Tunneling Barrier

In this work, we fabricate FeFETs with a TiN/Al2O3/Hf_0.5Zr_0.5O2/Al2O3/Hf_0.5Zr_0.5O2/SiOx/Si (MAFAFOS) gate-stack, utilizing Al2O3for both the tunneling dielectric layer (TDL) and gate interlayer (GIL). By using 2-nm TDL/3-nm GIL and reducing the unstable charges trapped at the GIL interface, we achieve a memory window (MW) of 9 V at an operating voltage of −13 +14 V and superior retention characteristics, with a 0.44% MW loss over 10 years. Quantification of the electric field across the TDL at Vg ~≈ ~0V indicates that the TDL functions as an additional charge barrier and raises the energy band of the adjacent ferroelectric layer, leading to improved retention. This work demonstrates the potential of the MAFAFOS gate-stacks for high-performance 3-D Fe-nandapplications.