Interfacial charge trapping in extrinsic Y₂O₃/SiO₂bilayer gate dielectric based MIS devices on Si(100)

Metal-insulator-semiconductor (MIS) structures based on an extrinsic Y 2 O 3 dielectric film on Si show high leakage currents due to roughness-related highly localized fields. Oxygen annealing increases the dielectric constant and strength and reduces leakage currents by transforming Y 2 O 3 (film)/Si(100) into a bilayer Y 2 O 3 (film)/SiO 2 /Si(100) dielectric structure. Evolution of interfacial SiO 2 causes generation of mid-gap interface states at E v + 0.23 eV and E v + 0.43 eV, which act as electron traps and are responsible for hysteresis effects in capacitance-voltage ( C - V ) and current-voltage ( I - V ) behaviour in the accumulation-inversion modes. The electron trapping reduces the cathodic field and causes lowering of the current and the shift in current to higher fields after successive ramps. The charge trapping effects cause varied and unstable C - V and I - V behaviour of MIS structures based on a Y 2 O 3 /SiO 2 bilayer gate dielectric. Its origin has been attributed to microstructure and defect state modification at the Y 2 O 3 film-Si interface. This limits its application in high-density dynamic random access memory and ultra-large-scale integration devices.