Evaluation of Fully-Integrated Switching Regulators for CMOS Process Technologies

This paper presents a feasible study of fully-integrated switching voltage regulators for power-optimized systems-on-chip (SoCs). In order to evaluate the power efficiency across a number of design variables, a compact macro-model of a regulator is created and validated. A key focus of the study is on the characteristics of the active and passive devices that are needed in order to maximize the efficiency of an on-chip regulator. With the macro-model, geometric programming is used to find the optimal characteristics for a given set of constraints such as load condition, process technology, and area. The achievable efficiencies for various current loads and across a range of technologies from 0.35-mum to 90-nm CMOS process are analyzed. The power efficiency is found to be strongly dependent on the inductor technology and over 70% efficiency is possible with advanced inductor technologies.