Two-dimensional transient simulations of drain lag and current collapse in GaN-based high-electron-mobility transistors

The intrinsic mechanisms of drain lag and current collapse in GaN-based high-electron-mobility transistors are studied by using two-dimensional numerical simulations. Simulated drain lag characteristics are in good agreement with reported experimental data. The dynamic pictures of trapping of hot electrons under drain-pulse voltages are discussed in detail. Hot-electron buffer-trapping effect plays an instrumental role in the current collapse mechanism. Polarization-induced interface charges have significant effect on the hot-electron buffer trapping and the current collapse can be weakened by increasing the interface charges. The trapped charges can accumulate at the drain-side gate edge, where the electric field significantly changes and gate-to-drain-voltage-dependent strain is induced, causing a notable current collapse. The simulation results show that the drain voltage range, beyond 5 V, is already in the field of the well-developed hot electron regime. The hot electrons can occupy a great number of traps at the drain-side gate edge leading to the current collapse at high drain bias (around 10 V), where the hot-electron trapping effect dominates. By considering quantum-well high-electron-mobility transistors, we find that better electron localization can reduce the current collapse.