Subthreshold channels at the edges of nanoscale triple-gate silicon transistors

The authors investigate the subthreshold behavior of triple-gate silicon field-effect transistors by low-temperature transport experiments. These three-dimensional nanoscale devices consist of a lithographically defined silicon nanowire surrounded by a gate with an active region as small as a few tens of nanometers down to 50×60×35nm3. Conductance versus gate voltage shows Coulomb blockade oscillations with a large charging energy due to the formation of a small potential well below the gate. According to dependencies on device geometry and thermionic current analyses, the authors conclude that subthreshold channels, a few nanometers wide, appear at the nanowire edges, hence providing an experimental evidence for the corner effect.