Implementation of a symmetrical double source SOI TFET for low power circuit application

Tunnel field-effect transistors (TFETs) are promising future candidates of ultra-low-power electronics because they have the potential to reach sub-60 mV/decade of subthreshold swing. Nevertheless, traditional TFET technologies have drawbacks associated with low ON-current and ambipolar conductivity, limiting their usefulness in the circuit. This paper introduces a symmetrical, double-source silicon-on-insulator, tunnel field-effect transistor (DSS SOI-TFET) to improve band to band tunneling and inhibit ambipolarity. The suggested design has two spatially symmetric sources regions that enhance both the area of the tunneling and carrier injection. The performance of devices is explored with the help of TCAD simulation in SILVACO Atlas and physical models with calibration. The findings show that the n-type and p -type DSS-TFETs have almost the same subthreshold swing in channel lengths of 5 nm to 13 nm, which facilitates the layout of the circuits with asymmetric design of the devices. At VDS = 0.1 V, the devices reach high I ON /I OFF ratios of about 10 13 and 10 12 with n-type and p -type TFETs, respectively. In order to assess the applicability from the circuit level, a TFET-based inverter is designed, which possesses a similar voltage transfer characteristic of a CMOS with a voltage gain of 16 and a noise margin of about 97% for VDD = 0.2 V. These findings show that the proposed DSS SOI-TFET has a potential to be used as the next-generation in ultra-low-power logic and RF applications.