Decision and clock recovery circuits for gigahertz optical fiber receivers in silicon NMOS

New design techniques for implementing a data and clock recovery circuit on a silicon NMOS monolithic IC employing 1-μm feature sizes, and operating at speeds greater than 2 Gbit/s are described. A clocked comparator can resolve a 60-mV peak-to-peak signal into logic levels at 2 Gbit/s. The circuit can tolerate a 100° phase margin between the incoming signal and the clock. An NRZ data rate of 4 Gbit/s may be resolved by two such multiplexed circuits following a preamplifier in the same technology. A VCO capable of operation at 2 GHz in a PLL, that does not require off-chip components, is also described. An observer loop concept is employed in the PLL to align the recovered clock signal with the incoming data.