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HMOS-CMOS, a new high-performance bulk CMOS technology, is described. This technology builds on HMOS II, and features high resistivity p-substrate, diffused n-well and scaled n- and p-channel devices of 2-/spl mu/m channel length and 400-/spl Aring/ gate oxide thickness. The aggressive scaling of n and p devices results in 350-ps minimum gate delay and 0.04-pJ power delay product. HMOS-CMOS is a single poly technology suitable for microprocessor and static RAM applications. A 4K static RAM test vehicle is described featuring fully CMOS six-transistor memory cell, a chip size of 19600 mil/SUP 2/, 75 /spl mu/W standby power, data retention down to a V/SUB cc/ voltage of 1.5 V and a minimum chip select and address access time of 25 ns.
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Yu et al. (1981) studied this question.
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