Presents one version of a 4K dynamic MOS random-access memory utilizing a 3 device/bit cell with an area of less than 2 mil/SUP 2//b, which is fabricated using an n-channel silicon gate MOS technology. The chip requires only a single phase clock and internally generates the multiphase timing required. Other than the single high voltage clock, all inputs and the output are TTL compatible.
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Abbott et al. (1973) studied this question.
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