Power SiC DMOSFET Model Accounting for Nonuniform Current Distribution in JFET Region

The main goal of this paper is development of a new circuit-based silicon carbide (SiC) DMOSFET model which physically represents the mechanism of current saturation in power SiC DMOSFET. Finite-element simulations show that current saturation for a typical device geometry is due to 2-D carrier distribution effects in the JFET region caused by current spreading from the channel to the JFET region. For high drain-source voltages, most of the voltage drop occurs in the current spreading region located in the JFET region close to the channel. A new model is proposed that represents the nonuniform current distribution in the JFET region using a nonlinear voltage source and a resistance network. Advantages of the proposed model are that a single set of equations describes operation in both the linear and saturation regions, and that it provides a more physical description of MOSFET operation.