A 100-MHz pipelined CMOS comparator

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Authors

Discussion

Achieves high-speed low-power comparison in single-supply CMOS; leaves open validation for cardiovascular instrumentation.

Intervention

VLSI-compatible CMOS comparator designed with a pipelined cascade of two regenerative sense amplifiers

Outcome

Maximum sampling rate and power dissipation

The authors designed a 100-MHz pipelined CMOS comparator that achieves high-speed voltage comparisons with low power dissipation.

Wu et al. (1988) studied this question.

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