An experimental 16-Mbit DRAM with reduced peak-current noise

An experimental 16-Mbit CMOS DRAM with die size of 8.52 X18.4 mm2has been developed. A trenched and saddled stack capacitor (TSSC) cell was invented, and storage capacitance of 30fF was obtained in a cell size of 1.65 x 3.339 ?spl mu/m2. Peak-current noise on the power buses during the sense-amplifier latching is suppressed by distributing large numbers of pull-down and pull-up drivers in memory core arrays. Two 4-V internal Vcc converters are used separately for peripheral and core array circuits. The reference voltage generator employs a bandgap reference circuit whose temperature stability is better than conventional MOS diode references.