A 2.7-4.5 V single chip GSM transceiver RF integrated circuit

This paper describes the design and implementation of a single-chip GSM (Global System for Mobile communications) transceiver RF integrated circuit. The chip includes the RF-to-baseband and baseband-to-RF (receive and transmit) functions, two fixed frequency PLL's, and a programmable frequency agile UHF synthesizer. It is implemented In a 1.5 /spl mu/m silicon bipolar process with 12 GHz NPN's and 110 MHz lateral PNP's. The receive path uses a single-IF solution including the RF mixer, quadrature demodulator, and variable gain IF amplifier on chip. The transmit path uses a direct-up architecture with an offset mixer and an output buffer capable of driving 0 dBm into 50 /spl Omega/. The frequency agile UHF synthesizer switches between receive and transmit modes and settles to within /spl plusmn/50 Hz (0.1 ppm) in less than 500 /spl mu/s. The UHF synthesizer includes all the synthesizer logic and the oscillator on chip. The only external components are the loop filter and tank circuit. This paper first explains the chip architecture decisions and block level descriptions. The transistor level circuit designs and layout are then discussed. Finally, the performance of the circuit performance versus the requirements is presented.