High density COS/MOS 1024-bit static random access memory

A static 1024/spl times/1 self-aligned silicon-gate COS/MOS random access memory (RAM) has been developed using `self-registry' techniques to achieve high packing density. The techniques developed permitted a 7500 transistor COS/MOS memory circuit to be fabricated in a 0.134/spl times/0.168 in/SUP 2/ chip, with a 13.4 mil/SUP 2/ six transistor cell. Such packing density is approximately five times that of conventional metal-gate COS/MOS circuits. The merits of fabricating such devices using an advanced process technique based on all ion-implanted diffusions to enhance yields have also been studied.