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A 64K-word by 1-bit CMOS static RAM with a 20-ns typical address access time and 70-mW active power dissipation is described. Third-generation CMOS (Hi-CMOSIII) technology is also described. In this technology, n-channel and p-channel MOS transistors having 1.3 /spl mu/m typical gate length and 1.3 /spl mu/m design rule are used. Good RAM performance is achieved by use of a pulsed-word-line technique and double p-well bipolar-CMOS circuitry.
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Minato et al. (1984) studied this question.
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