Source-Gated Transistors as BEOL-Compatible Devices for Monolithic 3D Integration: Architectures, Materials, and Spatial Validation

The semiconductor industry faces converging pressures from energy-constrained edge electronics and energy-bottlenecked high-performance computing, motivating heterogeneous monolithic three-dimensional (M3D) integration as a system-level response. M3D imposes a strict back-end-of-line (BEOL) thermal budget on upper-tier devices, restricting the channel materials and contact processes available and degrading conventional thin-film transistor performance. The source-gated transistor (SGT), in which drain saturation is set by gate-modulated injection across an engineered source barrier rather than by drain-side channel pinch-off, provides a device-level response: low saturation voltage, high output impedance, large intrinsic gain, and tolerance to channel-length variation, all achieved with moderate-mobility and nonideal-contact channel materials. This review organizes reported SGTs by source-barrier architecture and channel-material platform, develops a spatial characterization framework that complements electrical measurements for unambiguous identification of source-controlled operation, and surveys applications across standalone edge electronics and BEOL-compatible upper tiers in M3D stacks. Integrating non-volatile memory mechanisms into the source barrier further extends SGTs into a compute-in-memory and neuromorphic upper-tier role in which the voltage-invariant saturation current itself functions as a programmable, read-bias-robust state variable. Together, these considerations position SGTs as a flexible architectural primitive for heterogeneous M3D platforms that address the energy demands of both edge and high-performance computing.