Using a detailed memory failure cluster analysis we demonstrate a novel direct measurement of the charge collection efficiency ratio of N+ and P+ diffusions for 90 nm CMOS in the terrestrial neutron environment. For the first time, we have proved empirically that the Nwell junction is a strong barrier to charge sharing, and experimentally measured the ratio to be 4.5 for the 90 nm CMOS technology. This result provides a critical parameter for SEU circuit simulations. In addition, the accurate measurement of this parameter provides circuit designers a quantitative way to size the transistors based on their types for design hardening.
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Zhu et al. (2007) studied this question.
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