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Single-event upsets (SEUs) in static random access memories (SRAMs) are investigated using three-dimensional (3-D) full cell device simulations for tracks that do not cross the OFF n-channel MOSFET drain. These tracks are representative of the most probable geometrical cases when the ions are generated inside the device by nuclear reactions, and then address one important part of neutron- or protons-induced soft errors. It is found that the duration and magnitude of the ion-induced current pulse strongly depends on the track location. As a result, the flipping of the memory cell is delayed, and the critical charge involved during the upset is no longer constant. A linear relationship between the critical charge and the delay is found and is explained by the contribution of the ON p-channel MOSFET. The increase of the ion current pulse delay and broadening when the track is moved away from the drain is explained on the basis of the diffusion-collection mechanism. Indications on the size of the sensitive regions are derived.
Palau et al. (Sun,) studied this question.