Negative-Capacitance FET With a Cold Source

The subthreshold swing (SS) of a field-effect transistor (FET) is given by the body factor multiplied by the transport factor and has a limit of60 mV · ⁻¹at room temperature in the case of the MOSFET. To break this SS limit, the negative-capacitance FET (NC-FET) lowers the body factor by using a ferroelectric film in the gate stack, whereas the cold source FET (CS-FET) and the Dirac source FET (DS-FET) lower the transport factor by introducing an electronic bandgap or manipulating the density of states in the injecting source. In this work, we theoretically and computationally investigate the possibility of FETs with both NC and CS/DS so that both the body and transport factors are lowered simultaneously. The new device physics of the negative-capacitance CS-FET (NCCS-FET) is numerically investigated for 2-D monolayer black phosphorus (ML-BP) FETs with the Hf0.5Zr0.5O3ferroelectric material in the gate stack. The device characteristics of six different FETs, the conventional MOSFET, CS-FET, DS-FET, NC-FET, NCCS-FET, and NCDS-FET are calculated and compared. Overall, the NCCS-FET achieves an average SS of30.1 mV · ⁻¹and a minimum SS as low as7.21 mV · ⁻¹; its O N–O FF ratio is about four orders of magnitude higher than that of a conventional MOSFET. The combined effects of NC and CS more efficiently decrease power dissipation.