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Amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in active matrix displays and sensors, in which their operation is typically analog in nature. However, the TFT experiences a V/sub T/ shift with time under gate bias, and the need for a model of the V/sub T/ shift with variable gate bias is imperative for robust circuit design. A model for the V/sub T/ shift under constant and variable gate bias has been presented and agrees with measurement results. The developed model can be easily represented by circuit elements and incorporated into a circuit simulator. As a proof of concept, we use the model to predict the transients of a weighted voltage subtractor circuit.
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Sambandan et al. (2005) studied this question.
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