A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques

A 5 Gb/s source-synchronous signaling system was developed utilizing a new clock/data skew minimization technique. The method incorporates a transmit clock delay line and integrating receiver yielding an increased tolerance to high frequency transmit source jitter. The system has the potential to support rapid turn-on without the clock buffer latency of conventional source-synchronous systems. A second method to minimize clock distribution delays with embedded clocking via superposition of clock in the common-mode across two differential pairs was also explored. A test device was fabricated in TSMC's 40 nm LP CMOS process and performance measurements indicate substantial margin improvements, even when the matched source-synchronous system is subjected to realistic source SJ and independent PSIJ noise. Comparable performance was also achieved with embedded common-mode clocking with matched peak swings, indicating it as a potential solution for pin-constrained designs.