Technology Assessment of Through-Silicon Via by Using C–V and C–t Measurements

C-V characteristics of through-silicon vias (TSVs) manufactured in two different processing lines are compared to demonstrate the reproducibility of the TSV process module in terms of the minimum TSV depletion capacitance in the operating voltage region. TSV C-V and C-t measurements before and after thermocycling are employed for assessing the oxide liner and Ta barrier integrity of the TSV under the influence of temperature. It is observed that TSV C-V and C-t characteristics remain unchanged before and after thermocycling (1000 cycles).