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A new deep-level transient spectroscopy (DLTS) technique has been developed for the characterization of deep-level imperfection centers in silicon-on-sapphire (SOS) epitaxial layers, and is based on the use of conductance transients on MOSFET's. Both the distribution of trap levels with energy in the bandgap of silicon and the spatial distribution of levels in the epitaxial film have been obtained. This complete characterization of trapping levels allows process techniques to be developed to control and reduce their concentrations to acceptable levels in SOS technology.
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Chen et al. (1981) studied this question.
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