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The safe-operating-area (SOA) of large array device (LAD) is one of the most important factors affecting the device reliability. In this paper, the improvement of the electrical-SOA (E-SOA) and the thermal-SOA (T-SOA) by using an optional implantation layer for 5-V n-channel large array MOSFET has been investigated in a 0.15-μm bipolarCMOS-DMOS process. Experimental results showed that the secondary breakdown current (It2) is improved by 5 times, and a significant improvement is also observed in the E-SOA and the T-SOA boundary as compared to the original device. In addition, the impact of inserting additional layout pick-ups into the multiple-finger layout of large array MOSFET to the E-SOA, It2, and trigger voltage is also practically investigated in silicon for the LAD with a total width of 12000 μm.
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Nidhi et al. (2018) studied this question.
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