Graded buried-oxide engineering in vertically stacked SOI–GAA complementary FETs: a broadband DC and noise investigation

Vertically stacked complementary field-effect transistors (CFETs) offer a promising route to high-density CMOS scaling beyond the 14 nm node, but their tightly coupled architecture introduces parasitic capacitance, interlayer electrostatic coupling, and trap-assisted conduction that degrade both DC and noise performance. This work proposes and analyses a structurally optimized CFET that integrates a tri-layer multi-κ buried-oxide (BOX) stack composed of 18 nm SiO 2 + 7 nm Si 3 N 4 + 15 nm HfO 2 , evaluated against a baseline CFET without BOX through a self-consistent three-dimensional Synopsys Sentaurus TCAD framework. The device combines a bottom silicon-on-insulator (SOI) nMOS FinFET with a top SiGe (25% Ge) gate-all-around (GAA) pMOS nanosheet transistor sharing a common TiN gate. Hydrodynamic transport with piezo-stress mobility tensors, MLDA quantum corrections, and a complete Green-function diffusion plus flicker/GR noise model with a Gaussian trap distribution are solved over fourteen frequency decades (0.1–10 13 Hz, 3 points/decade). Simulation results show that the multi-κ BOX architecture raises I ON from 102.7 µA/µm to 110.2 µA/µm for the SOI nMOS and from 519.8 µA/µm to 542.3 µA/µm for the GAA pMOS, with OFF-state leakage suppressed by more than three orders of magnitude and I ON /I OFF ratios above 10 14 for the nMOS and approximately 6 × 10 8 for the pMOS. Subthreshold swing remains tightly controlled at 58–64 mV/dec (nMOS) and 68–82 mV/dec (pMOS), while threshold voltages stay balanced at 0.435–0.445 V and − 0.54 to − 0.57 V. Noise simulations predict a reduction in S id (f) for the nMOS and pMOS across the band, terminal noise correlation coefficients reduced into physically benign limits, and a 0.4–0.6 dB (nMOS) and 0.3–0.5 dB (pMOS) decrease in minimum noise figure (NF min ) at 10 GHz, while high-frequency intrinsic transport remains intact. The proposed multi-κ BOX CFET therefore offers a scalable platform for low-power, low-noise, and RF-compatible logic beyond the 14 nm node.