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This paper presents a monolithic comparator implemented in a 0.5-/spl mu/m SiGe heterojunction bipolar transistor (HBT) process. The SiGe HBT process provides HBT npn transistors with maximum f/sub T/ over 40 GHz and f/sub max/ over 55 GHz. The comparator circuit employs a resettable slave stage, which was designed to produce return-to-zero output data. Operation with sampling rates up to 5 GHz has been demonstrated by both simulation and experiments. The comparator chip attains an input range of 1.5 V, dissipates 89 mW from a 3-V supply, and occupies a die area of 407/spl times/143 /spl mu/m/sup 2/. The comparator is intended for analog-to-digital (A/D) conversion of 900 MHz RF signals.
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Gao et al. (1996) studied this question.
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