A dual-mode CMOS power amplifier (PA) with an integrated tunable matching network is presented. A switched capacitor is fully analyzed to implement a tunable matching network in terms of power-handling capability, tuning ratio, quality factor, and linearity. Based on the presented consideration, a 3.3-V 2.4-GHz fully integrated CMOS dual-mode PA is implemented in a 0.18-μm CMOS process. The PA has two power modes, high-power and low-power (LP), and each mode is optimally matched by the tunable matching network. The LP mode enables more than 50% dc current reduction from 0- to 10-dBm power range. The improved efficiency in this study is approximately twice that of other multimode CMOS PAs reported thus far.
No takes yet. Share an insight, caveat, or question.
Yoon et al. (2011) studied this question.
Synapse has enriched 2 closely related papers on similar clinical questions. Consider them for comparative context: