I/sup 2/L with a self-aligned double-diffused injector

Reports the structure topology, and characterization of integrated injection logic (I/SUP 2/L/MTL) with a self-aligned double-diffused injector. It is shown that using the new structure, a lateral p-n-p transistor with effective submicron base width can be realized even by using standard photolithographic techniques. One of the features of the approach is the high injection efficiency. Another feature is the high current gain capability for n-p-n transistors. A power delay product of 0.06 pJ, a propagation delay time of 10 ns at the power dissipation of 80 /spl mu/W, and a packing density of 420 gates/mm/SUP 2/ have been obtained by single layer interconnections of 6 /spl mu/m details. A J-K flip-flop with clear and preset terminals has been fabricated to demonstrate the superiority of S/SUP 2/L to conventional I/SUP 2/L.