Switched collector impedance memory

Bipolar memory cells capable of achieving as high a ratio of READ/WRITE current to standby current as 40:200 in contrast to the ratio of 0.8:8 obtainable by conventional memory cells are proposed. In a standby condition the collector impedance of the cells is high and when accessed the impedance is switched to a much lower value. The proposed device structures proficiently utilize such layers as pinched epitaxial layers or pinched base layers for the integration of high resistance or switched impedance within a minimum chip area. In breadboard tests the proposed memory cells exhibited an access time of less than 4 ns and a cycle time of less than 15 ns at standby power dissipation ranging from 50 to 200 /spl mu/W/bit. A 288-bit LSI, using one of the proposed device structures, has been fabricated to obtain an access time of 4 ns and a write time of 4 ns.