Interface trap conductance spectroscopy of a narrow-gap Hg1-xCdxTe (x approximately=0.2) MIS device

The observation of a pronounced double peak structure in the equivalent parallel conductance of a metal-insulator-semiconductor (MIS) device prepared on a Bridgman-grown x approximately=0.2 p-type Hg 1-x Cd x Te crystal passivated by an anodic oxide layer is reported. The first peak, placed in the depletion part of the conductance-voltage (G-V) curves, has been attributed to the response of single-level interface traps distributed over the semiconductor gap supposing band-bending fluctuations. The second peak, placed at the onset of strong inversion, is due to shunting of the minority carrier flow by the electrons coming from the inverted surface area beyond the gate. An order of magnitude enhancement of the structure measured on capacitance-voltage (C-V) and G-V curves below T approximately=10 K has been attributed to hole freezeout, leading to a substantially slower sample response and to an exponential increase of its series resistance. The tunnelling from acceptor states near the Fermi level to interface traps and/or to light hole states in the valence band becomes a competing mechanism to majority carrier response in the depletion and accumulation regions in that case.