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The processing, a.c. and d.c. characteristics of I/SUP 2/L structures integrated with common analog circuit elements are studied. Since the required breakdown voltage of the analog circuitry normally dictates the resistivity and thickness of the silicon epitaxial layer, the authors studied the parametric performance of the I/SUP 2/L structure for common linear circuit voltages. Design criteria, processing, and device performance are presented for I/SUP 2/L structures built on several different types of material. The I/SUP 2/L performance achieved in the linear compatible technology easily allowed a fan-out of four and gate propagation delay less than 50 ns with standard device breakdowns of 20 V; but fan-out is limited to three and gate delay to 100 ns for the process which attained 30-V breakdowns.
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Saltich et al. (1976) studied this question.
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